Clock synchronization is the process by which the frequencies of two separate system clock signals are synchronized together to prevent information loss between the two computational systems. For example, clock synchronization plays a central role in determining the quality of service provided between two systems, (e.g., for maintaining a particular quality of service for voice transmissions, for data transmissions to modems, for Fax transmissions, for TTY transmissions, for Bonded Video transmissions, etc).
Often times, there are multiple input clock signals that can be used as timing synchronization reference sources for a system clock of a computational system (e.g., data and voice E1/T1 trunks may provide clock synchronization signals to a computational system from various sources; moreover, a single computational system may have multiple E1/T1 trunks providing clock synchronization signals thereto). FIG. 1 shows a block diagram of a clock synchronizer 10 for a computational system (not shown), wherein the clock synchronizer receives multiple input reference clock signals (denoted herein as input reference clocks #1, #2, and #3), and outputs a system clock signal 14 for the computational system (this signal denoted herein as a system clock 14).
When a computational system is provided with multiple input reference clocks, switching between such reference clocks must be performed in a manner that guarantees the stability of the output system clock 14. In particular, most computational systems are known to have a limited capacity for operating as desired if there is a substantial abrupt change in system clock phase (especially since this would result in a instantaneous change in frequency).
Most common clock synchronization schemes include the use of a Digital Phase Locked Loop (DPLL) 30 (FIG. 2) along with some extra circuitry to provide clock switching. Basically the phase difference between the input reference clock #1 (FIG. 2), and the output system clock 14 is measured using a phase detector 32, and depending upon the direction and size of the (any) phase error detected, the frequency of the system clock 14 is increased or decreased by changing an input to a numerically controlled oscillator 34 (NCO) as one skilled in the art will understand. That is, the DPLL 30 synchronizes an output system clock 14 to the input reference clock #1 via use of a signal feedback connector 35. However, such a DPLL 30 does not facilitate or perform switching between two input reference clocks. Accordingly, support circuitry 36 (FIG. 3) is typically added in front of the phase detector 32 of the DPLL 30 in order to appropriately switch between two (or more) input reference clocks. Such support circuitry 36 generally includes a plurality of programmable delay circuits 38 (e.g., one for each of the input clock references #1 and #2) for generating “virtual” phase aligned versions of the input reference clocks. That is, at least one of the input reference clocks #1 or #2 (FIG. 3) has its phase and/or frequency adjusted by a corresponding one of the programmable delay circuits 38 so that the resulting “virtual” clocks signals (i.e., virtual input reference clocks #3 and #4) are phase aligned. Accordingly, once the virtual input reference clocks #3 and #4 are synchronized (i.e., phase aligned), switching between the two input reference clocks can proceed, wherein the support circuitry 36 gradually changes the virtual input reference clock #5 (FIG. 3) so that it becomes substantially a copy of the input reference clock signal that has been switched to. Accordingly, the clock signal input to the DPLL 30 does not change significantly during the switch, which in turn means that the output system clock 14 will not change abruptly.
There are, however, problems with such typical implementations of the circuitry 36. First, the programmable delay circuitry 38 is usually implemented using some type of tapped delay line 40 (FIG. 4). The tapped delay line 40 includes multiple flip-flops 42 (FIG. 4) and a proportionally sized multiplexer 43. Accordingly, tapped delay lines 40 are expensive because they require a flip flop for every phase step that is required, as one skilled in the art will understand. Thus, if a tapped delay line 40 operates at 20 MHz, and the input reference clock 44 (FIG. 4) frequency is 8 kHz, then in order to handle phase differences up to 180 degrees, approximately 1250 flip-flops 42 are required for each of the programmable delay circuits 38. Additionally, program logic (e.g., a multiplexer) must be supplied to control which tapped delay line 40 (i.e., programmable delay circuit 38 in FIG. 3) is to be activated, and extra logic is required for operating the compare 46 and control circuits 48 shown in FIG. 3.
Accordingly, it is desirable to have a less complex, less costly embodiment of a clock synchronizer. The proposed solution provides a method to keep the system clock stable while switching between two reference clocks with differing phases.